SK Hynix Unveils H-TPU Architecture
The rapid expansion of AI has fundamentally shifted data center performance bottlenecks. Specifically, these constraints now plague the memory and storage layers. Consequently, SK Hynix officially introduced the H-TPU (Hynix Transaction Processing Unit) architecture on October 12. This innovative design divides the processor by function to maximize operational efficiency. Furthermore, it overcomes the severe power and size limitations of traditional central processing units (CPUs).
Addressing AI Data Center Limitations
In Jae Koo serves as Vice President of SoC Design at SK Hynix. He delivered a compelling keynote address at the ISOCC 2026 conference in South Korea. During his presentation, he highlighted the structural limitations facing modern AI data centers. He noted that GPU performance and PCIe bandwidth double with every generation. However, the general-purpose CPU frequencies and control capabilities inside SSD controllers have hit an absolute wall.
The Problem with Traditional CPUs
He believes that traditional monolithic CPU architectures struggle to handle hundreds of detailed storage control functions. In the past, engineers merely forced CPU cores to increase performance. Sadly, this approach resulted in massive power waste and highly unpredictable pipeline delays. Therefore, SK Hynix launched its proprietary, ultra-lightweight transaction-specific processor, the H-TPU, to overcome these boundaries.
Understanding the H-TPU Technology
The H-TPU is definitely not a tensor accelerator for AI calculations. Instead, it serves as a specialized programmable processor. Designers created it specifically to control SSD data planes and process transactions. By abandoning reliance on a single massive CPU, developers successfully dismantled the control functions. Then, they divided the processor into highly efficient functional units. Finally, they distributed these units across dozens of compact TPU clusters.
Incredible Efficiency and Power Savings
In Jae Koo offered a detailed technical explanation regarding this innovation. He stated that the H-TPU utilizes a simplified four-stage pipeline. Furthermore, it completely excludes superscalar and out-of-order execution devices. Remarkably, it occupies merely a fraction of a standard CPU core’s physical area. At the same time, it consumes only about 2.5 percent of the standard power envelope.
He added another vital piece of information regarding operational efficiency. Only functional modules related to a specific task, such as writing data, actively operate. Meanwhile, unused modules immediately switch to their lowest power mode. Consequently, this brilliant mechanism drastically reduces the overall power consumption of the entire controller.
Future Applications and HBF Synergy
SK Hynix confidently plans to apply this H-TPU technology across its various NAND memory product lines. For instance, future implementations will include next-generation enterprise solid-state drive (eSSD) controllers. Afterward, engineers will integrate it into the upcoming ‘Storage Next’ AI storage architecture.
Additionally, SK Hynix anticipates profound results from this controller innovation. The company expects the H-TPU to combine seamlessly with its next-generation High Bandwidth Flash (HBF). SK Hynix will release this highly anticipated HBF technology next year. Ultimately, this powerful combination will generate immense synergistic effects across the industry.
